1. Field of the Invention
The present invention relates to integrated circuits, and particularly to integrated circuits with partial and/or complete immunity to failure modes associated with radiation exposure, and even more particularly to radiation hardening of integrated circuits including a memory array.
2. Description of the Related Art
CMOS circuits are enormously important to modern society as these devices are used to operate and control nearly every facet of daily life. CMOS circuits are relied upon to build up the electronic components which control critical electronic systems used to control commercial aircraft, automobiles, medical equipment, embedded medical devices, industrial machinery, high speed trains, oil well drilling equipment, communication networks, satellites, and defense systems, to name a few. The common denominator that is critical for all the CMOS circuit components used in the aforementioned electronic equipment is error-free operation. Additionally, as CMOS circuits scale down to smaller and smaller critical dimensions and the operation voltage is reduced, the sensitivity to “soft errors” which stem from radiation single event effects (SEE) is increasing. CMOS circuits now have to be carefully chosen for system use with consideration given to the physical operating environment and its reliability to SEE in those particular environments. Digital electronics critically depend on binary values (i.e., a digital “0” or “1”) for each critical bit of an instruction word. For modern software and hardware systems, each instruction word may include up to 32 (or more) individual state bits, each of which can take on the value of either 0 or 1.
A modern microprocessor will execute each distinct instruction word as it computes the program instructions in sequence. The software program instructions are coded into their digital values (binary 0 and 1) by the system compiler (software) before execution by the digital hardware to yield an output value. As such, properly maintaining each 0 or 1 bit value used in digital word is critically important for reliable system behavior. It is in the context of critical binary bit state that the importance “soft errors” now becomes more apparent.
Certain extreme environments (where CMOS circuits need to operate) exist which will significantly increase the risk for individual bit errors, which in turn can significantly affect the reliability of the electronic control system. These extreme environments are principally:                System operating temperature ranging from extreme cold (−55 C) to extreme hot (200 C);        Supply voltage variations (+/−20%) used to power the system; and        Radiation effects (heavy ion, neutron, proton, electron, gamma ray, cosmic ray).        
A majority of CMOS integrated circuits operate in non-extreme environments and thus are not at high risk for soft errors and are known to operate reliably. Most commercial semiconductor manufacturers rate the reliability of their CMOS circuit components at 20 FITS or less. The Failure-In-Time (FIT) is the industry benchmark for reliability. A processor rated at 20 FITs would be expected to execute one billion instructions with no more than 20 instruction failures. In this context, time is an indeterminate value and the quotient (20 FITS) is rather the number of instruction failures (ranging from 0 to 20) which would be expected to occurring for 1 billion executed digital words in a particular chip. The time enters into the context as a function of how long it would take to execute 1 billion instructions for a particular chip. As electronic systems range in performance from slow to high, the time between failures can vary from seconds to much longer periods. However, for CMOS circuits which operate in extreme environments, the FIT rates are dramatically increased to the extent that acceptable (error-free) reliable operation becomes nearly impossible. CMOS chips operating in such extreme environments need to be better designed, and the silicon isolation performance needs to be better engineered, to avoid both a single-bit failure or logic network failure which can stem from similar physical electrical effects.